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| www.ti.com 8 TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 ENHANCED, LOW INPUT VOLTAGE MODE SYNCHRONOUS BUCK CONTROLLER FEATURES D D D D Operating Input Voltage 2.25 V to 5.5 V Output Voltage as Low as 0.7 V 1% Internal 0.7 V Reference Predictive Gate Drive N-Channel MOSFET Drivers for Higher Efficiency Circuit Current Limit DESCRIPTION The TPS4002x family of dc-to-dc controllers are designed for non-isolated synchronous buck regulators, providing enhanced operation and design flexability through user programmability. The TPS4002x utilizes a proprietary Predictive Gate Drive technology to minimize the diode conduction losses associated with the high-side and synchronous rectifier N-channel MOSFET transistions. The integrated charge pump with boost circuit provides a regulated 5-V gate drive for both the high side and synchronous rectifier N-channel MOSFETs. The use of the Predictive Gate Drive technology and charge pump/boost circuits combine to provide a highly efficient, smaller and less expensive converter. Design flexibility is provided through user programmability of such functions as: operating frequency, short circuit current detection thresholds, soft-start ramp time, and external synchronization frequency. The operating frequency is programmable using a single resistor over a frequency range of 100 kHz to 1 MHz. Higher operating frequencies yield smaller component values for a given converter power level as well as faster loop closure. D Externally Adjustable Soft-Start and Short D Programmable Fixed-Frequency 100 KHz-to-1 MHz Voltage-Mode Control D Source-Only Current or Source/Sink Current D Quick Response Output Transient Comparators with Power Good Indication Provide Output Status D 16-Pin PowerPAD Package APPLICATIONS D D D D D Networking Equipment Telecom Equipment Base Stations Servers DSP Power VDD VDD 2.25 V - 5.5 V 1 VOUT 2 3 4 5 6 7 8 TPS40020 ILIM/ SYNC VDD OSNS FB COMP SS/SD RT SGND BOOT1 16 HDRV SW BOOT2 PVDD LDRV PGND 15 14 13 12 11 10 VOUT PWRGD 9 UDG-02094 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD and Predictive Gate Drive are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2004, Texas Instruments Incorporated TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 www.ti.com DESCRIPTION (CONTINUED) The short circuit current detection is programmable through a single resistor, allowing the short circuit current limit detection threshold to be easily tailored to accommodate different size (RDS(on)) MOSFETs. The short circuit current function provides pulse-by-pulse current limiting during soft-start and short term transient conditions as well as a fault counter to handle longer duration short circuit current conditions. If a fault is detected the controller shuts down for a period of time determined by six (6) consecutive soft-start cycles. The controller automatically retries the output every seventh (7th) soft-start cycle. In addition to determining the off time during a fault condition, the soft-start ramp provides a closed loop controlled ramp of the converter output during startup. Programmability allows the ramp rate to be adjusted for a wide variety of output L-C component values. The output voltage transient comparators provide a quick response , first strike, approach to output voltage transients. The output voltage is sensed through a resistor divider at the OSNS pin. If an overvoltage condition is detected the HDRV gate drive is shut-off and the LDRV gate drive is turned on until the output is returned to regulation. Similarly, if an output undervoltage condition is sensed the HDRV gate drive goes to 95% duty cycle to pump the output back up quickly. In either case, the PowerGood open drain output pulls low to indicate an output voltage out of regulation condition. The PowerGood output can be daisy-chained to the SS/SD pin or enable pin of other controllers or converters for output voltage sequencing. The transient comparators can be disabled by simply tying the OSNS pin to VDD. The TPS4002x can be externally synchronized through the ILIM/SYNC pin up to 1.5x the free-running frequency. This allows multiple contollers to be synchronized to eliminate EMI concerns due to input beat frequencies between controllers. INTERNAL BLOCK DIAGRAM VDD OSNS 2 3 VDD 0.719 V VDD SS ACTIVE 0.659 V CHARGE PUMP 13 12 16 PREDICTIVE GATE DRIVE(tm) PWM LOGIC UVLO DRV FAULT 10 CLK SS ACTIVE CURRENT LIMIT COMPARATOR OC IRT - + SD 0.28 V SYNC UVLO UVLO + + 1V 1 ILIM/SYNC VDD PGND 11 LDRV DRV 15 14 PVDD BOOT2 PVDD BOOT1 HDRV SW PWRGD 9 FB 4 0.69 V + + UVLO OSC CLK PWM COMP 5 RT 7 IRT ISS SS/SD 6 SOFT START FAULT COUNTER DCHG UVLO SGND 8 VDD DISABLE VDD 1.4 V UDG-02092 2 www.ti.com TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA -40C to 85C (1) See page 7 for explanation. (2) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS40020PWPR). See the application section of the data sheet for PowerPAD drawing and layout information. LOAD CURRENT(1) SOURCE SOURCE/SINK PACKAGE Plastic HTSSOP (PWP)(2) Plastic HTSSOP (PWP)(2) PART NUMBER TPS40020PWP TPS40021PWP ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(4) TPS4002X SS/SD, VDD, PVDD, OSNS BOOT2, BOOT1 Input voltage range, VIN SW SWT (SW transient < 50 ns) FB, ILIM Output voltage range, VOUT Sink current, IS Operating virtual junction temperature range, TJ Storage temperature, Tstg COMP, PWRGD, RT PWRGD -0.3 to 6 VSW + 6 -3.0 to 10.5 -5 -0.3 to 6.0 -0.3 to 6 10 -40 to 125 -55 to 150 C C mA V UNIT Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 (4) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN Input voltage, VIN Operating junction temperature, TJ PWP PACKAGE(5)(6) (TOP VIEW) 2.25 -40 NOM MAX 5.5 85 UNIT V C ILIM/SYNC VDD OSNS FB COMP SS/SD RT SGND 1 2 3 4 5 6 7 8 THERMAL PAD 16 15 14 13 12 11 10 9 BOOT1 HDRV SW BOOT2 PVDD LDRV PGND PWRGD (5) For more information on the PWP package, refer to TI Technical Brief, Literature No. SLMA002. (6) PowerPADt heat slug must be connected to SGND (Pin 8), or electrically isolated from all other pins. 3 TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 www.ti.com ELECTRICAL CHARACTERISTICS TJ = -40C to 85C, TJ = TA, VDD = 5.0 V (unless otherwise noted) PARAMETER INPUT SUPPLY VDD VPVDD IDD Input voltage range, VDD PVDD pin voltage Switching current Quiescent current Shutdown current Minimum on-voltage VUVLO Hysteresis 2.25 V VDD 5.00 V, RT = 69.8 k 2.25 V VDD 5.00 V, RT = 34.8 k VPEAK-VVAL OSCILLATOR 425 800 0.80 0.24 VOSNS = VDD, RT = 34.8 k, VDD = 3.3 V, FB = 0 V VOSNS = VDD, RT = 70 k, VDD = 5.0 V, FB = 0 V 500 950 0.93 0.31 575 1100 1.07 0.41 V kHz fOSC Accuracy VDD = 3.3 V 500 kHz, No load on HDRV, LDRV FB = 0.8 V SS/SD = 0 V, Outputs OFF 1.95 80 2.25 4.9 3.5 2.0 0.38 2.05 130 5.50 5.2 5.0 3.0 1.00 2.15 200 V mV mA V TEST CONDITIONS MIN TYP MAX UNIT VRAMP Ramp voltage VVAL Ramp valley voltage PWM 85% 90% 94% 95% 0% 250 ns 0.697 130 0.15 V nA V mA MHz dB 215 20 300 ns cycles VDD 3.3 5.4 V A A mV dMAX Maximum duty cycle dMIN tMIN VFB IBIAS VOH VOL IOH IOL GBW Minimum duty cycle Minimum HDRV on-time(2) Feedback input voltage Input bias current High-level output voltage Low-level output voltage High-level output source current Low-level output sink current Gain bandwidth(1) IOH = 0.5 mA, VFB = GND IOL = 0.5 mA, VFB = VDD VFB = GND VFB = VDD 2.0 3 3 5 55 2.25 V VDD 5.00 V, RT = 69.8 k VDD = 3.3 V 165 -20 -40C TA 85C, 2.25V VDD 5.00V 0.685 ERROR AMPLIFIER 0.690 30 2.5 0.08 7 8 10 85 190 0 200 140 6 2 2.0 AOL Open loop gain(1) CURRENT LIMIT ISINK VOS tON tON tSS VILIM Current limit sink current Current limit offset voltage Minimum HDRV on-time in overcurrent Switch leading-edge blanking pulse time(1) Soft-start cycles Current limit input voltage range SOFT START ISS Soft-start source current Outputs = OFF (1) Ensured by design. Not production tested. (2) Operation below the minimum on-time could result in overlap of the HDRV and LDRV outputs. 4 www.ti.com TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 ELECTRICAL CHARACTERISTICS (continued) TJ = -40C to 85C, TJ = TA, VDD = 5.0 V (unless otherwise noted) PARAMETER SHUTDOWN VSD VEN Shutdown threshold voltage Device enable threshold voltage V(BOOT1) - V(SW) = 3.3 V, ISOURCE = 100mA V(BOOT1) - V(SW) = 3.3 V, ISINK =100mA PVDD = 3.3 V, ISOURCE =100 mA PVDD = 3.3 V, ISINK =100 mA 0.22 0.25 0.26 0.28 0.29 0.32 V TEST CONDITIONS MIN TYP MAX UNIT OUTPUT DRIVER RHDHI High-side driver pull-up resistance 1.0 0.8 1.0 0.45 2.5 1.5 2.5 0.80 15 10 CLOAD = 1 nF 15 10 165 15 VDD = 5.0 V, VDD = 5.0 V, VDD = 5.0 V, ISOURCE =10 mA ISOURCE =10 mA ISOURCE =10 mA 2.8 2.8 2.9 6.6 5.6 5.9 10.4 8.4 8.9 5.0 3.0 5.0 1.50 35 25 35 25 ns RHDLO High-side driver pull-down resistance RLDHI RLDLO tLRISE tLFALL tHRISE tHFALL Low-side driver pull-up resistance Low-side driver pull-down resistance Low-side driver rise time Low-side driver fall time High-side driver rise time High-side driver fall time Shutdown temperature(1) Hysteresis(1) RDS(on) VDD to BOOT2 RDS(on) BOOT2 to PVDD THERMAL SHUTDOWN TSD C CHARGE PUMP RVB2 RB2P RPB1 RDS(on) PVDD to BOOT1 POWER GOOD VPGD Pull-down voltage Output sense high to power good low delay tONHPL time Output sense low to power good low delay tONLPL time tSDHPH Shutdown high to power good high delay time tSDLPL Shutdown low to power good low delay time Output sense high to nominal to power good tONHPH high delay time Output sense low to nominal to power good tONLPH high delay time TRANSIENT COMPARATORS Overvoltage output threshold voltage VOV VUV Hysteresis Undervoltage output threshold voltage Hysteresis VDIS OSNS minimum disable voltage (1) Ensured by design. Not production tested. VOSNS = 0.8 V, IPWRGD =0.5 mA, VDD = 3.3 V 0.7 V VOSNS 0.8 V, IPWRGD =0.5 mA, VDD = 3.3 V 0.6 V VOSNS 0.7 V, IPWRGD =0.5 mA, VDD = 3.3 V VOSNS = 0.7 V, IPWRGD =0.5 mA, VDD = 3.3 V, 0.0 V VSS/SD 0.4 V VOSNS = 0.7 V, IPWRGD =0.5 mA, VDD = 3.3 V, 0.0 V VSS/SD 0.4 V 0.7 V VOSNS 0.8 V, IPWRGD =0.5 mA, VDD = 3.3 V 0.6 V VOSNS 0.7 V, IPWRGD =0.5 mA, VDD = 3.3 V 50 6 6 2 0.5 140 140 90 10 10 4 1.5 500 500 140 14 14 mV s s 6 3.0 1000 ns 1000 23 8 Referenced to VFB -37 8 Referenced to VDD 0.5 29 15 -31 15 35 22 -25 22 V mV 5 TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = -40C to 85C, TJ = TA, VDD = 5.0 V (unless otherwise noted) PARAMETER SYNCHRONIZATION VENSY VBLNK Synchronization enable low threshold voltage Synchronization current limit enable threshold voltage Referenced to VDD -0.7 35 -200 LDRV OFF-to-HDRV ON LDRV OFF-to-HDRV ON HDRV OFF-to-LDRV ON HDRV OFF-to-LDRV ON 40 2.5 55 2.2 65 4.5 80 5.0 90 6.2 105 6.5 ns 50 0.7 V ns mV TEST CONDITIONS MIN TYP MAX UNIT tMIN Minimum synchronization input pulse width PREDICTIVE DELAY VSWP tLDHD tHDLD Sense voltage to modulate delay Maximum delay modulation Counter delay/bit time Maximum delay modulation Counter delay/bit time Sense voltage to turn off rectifier MOSFET RECTIFIER ZERO CURRENT COMPARATOR VSW TPS40020 LDRV output = OFF -5 -2.5 150 2 mV ns tZBLNK Zero current blanking time(1) (1) Ensured by design. Not production tested. TERMINAL FUNCTIONS TERMINAL NAME BOOT1 BOOT2 COMP FB HDRV NO. 16 13 5 4 15 I/O I I O I O DESCRIPTION This pin provides a bootstrapped supply for the high side FET driver, enabling the gate of the high side FET to be driven above the input supply rail. Connect a capacitor from this pin to the SW pin. This pin provides a secondary bootstrapping necessary for generation of PVDD. Connect a capacitor from this pin to SW. Output of the error amplifier. Refer to Electrical Characteristics table for loading constraints. Inverting input of the error amplifier. In normal operation, VFB is equal to the internal reference level of 690 mV. The gate drive output for the high side N-channel MOSFET switch is bootstrapped to near PVDD for good enhancement of the high-side switch. The HDRV switches from BOOT1 to SW. The current limit pin is used to set the current limit threshold. A current sink from this pin to GND sets the threshold voltage for output short circuit current across a resistor connected to VDD. Synchronization is accomplished by pulling IMAX to less than 1 V for a period greater than the minimum pulse width and then releasing. An open collector or drain device should be used. These pulses must be of higher frequency than the free running frequency of the local oscillator. Gate drive output for the low-side synchronous rectifier N-channel MOSFET. LDRV switches from PVDD to PGND. The output sense pin is connected to a resistor divider from VOUT to GND (identical to the main feedback loop) and is used to sense power good condition and provides reference for the transient comparators. Power (high-current) ground used by LDRV. Power good. This is an open-drain output which connects to the supply via an external resistor. This pin is the regulated output of the charge-pump and provides the supply voltage for the LDRV driver stage. PVDD also drives the bootstrap circuit which generates the voltage on BOOT1. External pin for programming the oscillator frequency. Connnected a resistor between this pin and GND. Signal ground The soft-start/shutdown pin provides user programmable soft-start timing and shutdown capability for the controller. This pin, used for overcurrent, zero-current, and in the anti-cross conduction sensing is connected to the switched node on the converter. Output short circuit is detected by sensing the voltage at this pin with respect to VDD while the high-side switch is on. Zero current is detected by sensing the pin voltage with respect to ground when the low-side rectifier MOSFET is on. Power input for the device. Maximum voltage is 5.5 V. De-coupling of this pin is required. ILIM/SYNC 1 I LDRV OSNS PGND PWRGD PVDD RT SGND SS/SD 11 3 10 9 12 7 8 6 O O O - O I - I SW VDD 6 14 2 I I www.ti.com TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 APPLICATION INFORMATION The TPS4002x series of devices are low-input voltage, synchronous, voltage mode-buck controllers. A typical application circuit is shown in Figure 1. These controllers are designed to allow construction of high-performance dc-to-dc converters with input voltages from 2.25 V to 5.5 V, and output voltages as low as 690 mV. Using a top side N-channel MOSFET for the primary buck switch results in lower switch resistance for a given gate charge. The device controls the delays from main switch off to rectifier turn on and from rectifier turn off to main switch turn on in a way that minimizes diode losses (both conduction and recovery) in the synchronous rectifier. The reduction in these losses is significant and can mean that for a given converter power level, smaller FETs can be used, or that heat sinking can be reduced or even eliminated. The TPS40021 is the controller of choice for most general purpose synchronous buck designs, operating in two quadrant mode (i.e. source or sink current) full time. This choice provides the best performance for output voltage load transient response over the widest load current range. The TPS40020 operates in single quadrant mode (source current only) full time, allowing the paralleling of converters. Single quadrant operation ensures one converter does pull current from a paralleled converter. A converter using one of these controllers emulates a non-synchronous buck converter at light loads. When current in the output inductor attempts to reverse, an internal zero-current detection circuit turns OFF the synchronous rectifier and causes the current flow in the inductor to become discontinuous. At average load currents greater than the peak amplitude of the inductor ripple current, the converter returns to operation as a synchronous buck converter to maximize efficiency. The controller provides for a coarse short circuit current-limit function that provides pulse-by-pulse current limiting, as well as integrates short circuit current pulses to determine the existence of a persistant fault state at the converter output. If a fault is detected, the converter shuts down for a period of time (determined by six soft-start cycles) and then restarts. The current-limit threshold is adjustable with a single resistor connected from VDD to the ILIM/SYNC pin. This overcurrent function is designed to protect against catastrophic faults only, and cannot be guaranteed to protect against all overcurrent conditions. The controller implements a closed-loop soft start function. Startup ramp time is set by a single external capacitor connected to the SS/SD pin. The SS/SD pin also doubles as a shutdown function. VOLTAGE REFERENCE The bandgap cell is designed with a trimmed, curvature corrected (< 1%) 0.69-V output, allowing output voltages as low as 690 mV to be obtained. Oscillator The ramp waveform is a saw-tooth form at the PWM frequency with a peak voltage of 1.25 V, and a valley of 0.3 V. The PWM duty cycle is limited to a maximum of 97%, allowing the bootstrap and charge pump capacitors to charge during every cycle. 7 TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 www.ti.com APPLICATION INFORMATION Bootstrap/Charge Pump The TPS4002X series includes a charge pump to boost the drive voltage to the power MOSFET's to higher levels when the input supply is low. A capacitor connected from PVDD to PGND is the storage cap for the pump. A capacitor connected from SW to BOOT2 gets charged every switching cycle while LDRV is high and its charge is dumped on the PVDD capacitor when HDRV goes high. An internal switch disables the charge pump when the voltage on PVDD reaches approximately 4.8 V and enables pumping when PVDD falls to approximately 4.6 V. The high-side driver uses the capacitor from SW to BOOT1 as its power supply. When SW is low, this capacitor charges from the PVDD capacitor. When the SW pin goes high, this capacitor provides above-rail drive for the high-side N-channel FET. PVDD, BOOT1 and BOOT2 are pre-charged to the VDD voltage during a shutdown condition. For low-input voltage converters, utilizing higher gate threshold voltage MOSFETs, it may be necessary to add an Schottky diode from VDD (anode) to BOOT1 to guarantee sufficient voltage for initial start up. Once switching starts the charge pump reverses bias on the Schottky diode. When operating the TPS40020 under no load or extremely light-load conditions the controller will be operating in discontinuous Mode (DCM); reverse current is prevented from flowing in the synchronous rectifier. In DCM the on times for both the HDRV and LDRV pulses can become too narrow to provide adequate charging of PVDD and BOOT1 outputs, causing their voltages to collapse. Insufficient PVDD and BOOT1 voltages prevent the external MOSFETS from becomming fully enhanced, causing loss of converter output regulation. Schottky diodes from VIN (anode) to PVDD, and VIN (anode) to BOOT1, as well as a pre-load can be added to maintain PVDD and BOOT1 at voltage levels sufficient enough to fully enhance the external MOSFETs. The amount of pre-load typically ranges from 50 mA to 100 mA depending on operating conditions and external MOSFET selection. Drivers The HDRV and LDRV MOSFET drivers are capable of driving gate-to-source voltages up to 5.0 V. Using appropriate MOSFETs, a 25-A converter can be achieved. The LDRV driver switches between VDD and ground, while the HDRV driver is referenced to SW and switches between BOOT1 and SW. The maximum voltage between BOOT1 and SW is 5.0 V when PVDD is in regulation. 8 www.ti.com VDD 3.3 V C10 330 F TPS4002XPWP C2 1 F 16 Q1 Si7858DP 1 2 VDD HDRV 3 SW 4 C15 47 pF BOOT2 13 12 11 10 9 R9 10 k C3 10 F C17 15 nF Q2 Si7880DP + R10 2.2 5 R7 30.1 k 6 PGND 7 PWRGD 8 PWP SGND RT SS/SD LDRV R4 118 k C13 0.022 F C14 2200 pF COMP PVDD C11 1 F FB 14 L1 0.75 F R6 10 k OSNS 15 ILIM/SYNC BOOT1 C11 22 F C12 22 F + R3 1.5 k + + C8 330 F C9 330 F R5 8.66 k C4 470 F + C5 470 F + C6 470 mF C7 10 F 1.25 V 20 A APPLICATION INFORMATION Figure 1. Typical Application C16 R8 1800 pF 2.87 k R1 8.66 k R2 10 k SLUS535B - MARCH 2003 - REVISED JANUARY 2004 TPS40020 TPS40021 UDG-03031 9 TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 www.ti.com APPLICATION INFORMATION Synchronous Rectification and Predictive Delay In a normal buck converter, when the main switch turns off, current is flowing to the load in the inductor. This current cannot be stopped immediately without using infinite voltage. To give this current a path to flow and maintain voltage levels at a safe level, a rectifier or catch device is used. This device can be either a plain diode, or it can be a controlled active device if a control signal is available to drive it. The TPS4002X provides a signal to drive an N-channel MOSFET as a rectifier. This control signal is carefully coordinated with the drive signal for the main switch so that there is absolute minimum dead time from the time that the rectifier FET turns off and the main switch turns on, and minimum delay from when the main switch turns off and the rectifier FET turns on. This TI-patented function, predictive delay, uses information from the current switching cycle to adjust the delays that are used for the next cycle. Figure 2 shows the switch-node voltage waveform for a synchronously rectified buck converter. Illustrated are the relative effects of a fixed delay drive scheme (constant, pre-set delays for the turnoff to turn on intervals), an adaptive delay drive scheme (variable delays based upon voltages sensed on the current switching cycle) and the predictive delay drive scheme. Note that the longer the time spent in diode conduction during the rectifier conduction period, the lower the efficiency. Also, not shown in the figure, is the fact that the predictive delay circuit can actually prevent the body diode from becoming forward biased at all while at the same time avoiding cross conduction or shoot through. This results in a significant power savings when the main FET turns on. There is no reverse recovery loss in the body diode of the rectifier FET. GND Channel Conduction Body Diode Conduction Fixed Delay Adaptive Delay Predictive Delay UDG-01144 Figure 2. Switch Node Waveforms for Synchronous Buck Converter 10 www.ti.com TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 APPLICATION INFORMATION Output Short Circuit Protection Output short circuit protection in the TPS4002x is sensed by looking at the voltage across the main FET while it is on. If the voltage exceeds a pre-set threshold, the current pulse is terminated, and a counter inside the device is incremented. If this counter fills up, a fault condition is declared and the chip disables switching for a period of time and then attempts to restart the converter with a full soft-start cycle. The more detailed explanation follows. In each switching cycle, a comparator looks at the voltage across the top side FET while it is on. If the voltage across that FET exceeds a programmable threshold voltage, then the current switching pulse is terminated and a 3-bit counter (eight counts) is incremented by one count. If during the switching cycle the top side FET voltage does not exceed a preset threshold, then this counter is decremented by one count. (The counter does not wrap around from seven to zero or from zero to seven). If the counter reaches a full count of seven, the device declares that a fault condition exists at the output of the converter. In this state, switching stops and the soft-start capacitor is discharged. The counter is decremented by one by the soft start cap discharge. When the soft-start capacitor is fully discharged, the discharge circuit is turned off and the cap is allowed to charge up at the nominal charging rate, When the soft-start capacitor reaches approximately 1.3 V, it is discharged again and the overcurrent counter is decremented by one count. The capacitor is charged and discharged, and the counter decremented until the count reaches zero (a total of six times). When this happens, the outputs are again enabled as the soft-start capacitor generates a reference ramp for the converter to follow while attempting to restart. During this soft-start interval (whether or not the controller is attempting to do a fault recovery or starting for the first time), pulse-by-pulse current limiting is in effect, but overcurrent pulses are not counted to declare a fault until the soft-start cycle has been completed. It is possible to have a supply try to bring up a short circuit for the duration of the soft-start period plus seven switching cycles. Power stage designs should take this into account if it makes a difference thermally. Figure 3 shows the details of the overcurrent operation. (+) VTS (-) Internal PWM Overcurrent Threshold Voltgage VTS 0V External Main Drive Normal Cycle Overcurrent Cycle UDG-03029 Figure 3. Switch Node Waveforms for Synchronous Buck Converter 11 TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 www.ti.com APPLICATION INFORMATION Figure 4 shows the behavior of key signals during initial startup, during a fault and a successfully fault recovery. At time t0, power is applied to the converter. The voltage on the soft-start capacitor (VCSS) begins to ramp up At t1, the soft-start period is over and the converter is regulating its output at the desired voltage level. From t0 to t1, pulse-by-pulse current limiting was in effect, and from t1 onward, overcurrent pulses are counted for purposes of determining if a fault exists. At t2, a heavy overload is applied to the converter. This overload is in excess of the overcurrent threshold, the converter starts limiting current and the output voltage falls to some level depending on the overload applied. During the period from t2 to t3, the counter is counting overcurrent pulses and at time t3 reaches a full count of 7. The soft-start capacitor is then discharged, the outputs are disabled, the counter decremented, and a fault condition is declared. VDD 9 1.3 V 9 0.6 V VCSS 0.6 V FAULT ILOAD VOUT t0 Counter t1 0 t2 t3 6 t4 5 t5 4 t6 3 t7 2 t8 1 t9 t10 0 t 1 2 3 4 5 6 7 cycles UDG-03187 Figure 4. Overcurrent/Fault Waveforms When the soft-start capacitor is fully discharged, it begins charging again at the same rate that it does on startup, with a nominal 3-A current source. As the capacitor voltage reaches full charge, it is discharged again and the counter is decremented by one count. These transitions occur at t3 through t9. At t9, the counter has been decremented to zero. Now the fault logic is cleared, the outputs are enabled and the converter attempts to restart with a full soft-start cycle. The converter comes into regulation at t10. The internal SS signal is a diode drop below VCSS. When VCSS reaches one diode drop above ground, (0.6 V) the output (VOUT) begins it's soft-start ramp. 12 www.ti.com TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 APPLICATION INFORMATION Setting the Short Circuit Current Limit Threshold Connecting a resistor from VDD to ILIM sets the current limit. A current sink in the chip causes a voltage drop across the resistor connected to ILIM. This voltage drop is the short circuit current threshold for the part. The current that the ILIM pin sinks is dependent on the value of the resistor connected to RT and is given by: I ILIM + 19.0 0.69 V RT (1) The tolerance of the current sink is too loose to do an accurate current limit. The main purpose is for hard fault protection of the power switches. Given the tolerance of the ILIM sink current, and the RDS(on) range for a MOSFET, it is generally possible to apply a load that thermally damages the converter. This device is intended for embedded converters where load characteristics are defined and can be controlled. A small capacitor can be added between ILIM and VDD for filtering. However, capacitors should not be used if the synchronization function is to be used. Soft-Start and Shutdown The soft-start and shutdown functions are common to the SS/SD pin. The voltage at this pin is the controlling voltage sent to the error amplifier during startup. This reduces the transient current required to charge the output capacitor at startup, and allows for a smooth startup with no overshoot of the output voltage. A shutdown feature can be implemented as shown in Figure 5. 3.3 A 6 CSS SHUTDOWN TPS4002x SS/SD Figure 5. Shutdown Implementation Switching Frequency The switching frequency is programmed by a resistor from RT to SGND. Nominal switching frequency can be calculated by: R T (kW) + 37.736 10 * 5.09 (kW) f OSC(kHz) 3 (2) 13 TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 www.ti.com APPLICATION INFORMATION Synchronization The TPS4002x can be synchronized to an external reference frequency higher than the free running oscillator frequency. The recommended method is to use a diode and a push pull drive signal as shown in Figure 6. PREFERRED VDD ALTERNATE VDD TPS4002XPWP Minumize Output/Stray Capacitance on ILIM Node TPS4002XPWP 1 2 ILIM/SYNC VDD 1 2 ILIM/SYNC VDD UDG-03032 Figure 6. Synchronization Methods This design allows synchronization up to the maximum operating frequency of 1 MHz. For best results the nominal operating frequency of a converter that is to be synchronized should be kept as close as practicable to the synchronization frequency to avoid excessive noise induced pulse width jitter. A good target is to shoot for the free run frequency to be 80% of the synchronized frequency. This ensures that the synchronization source is the frequency determining element in the system and not to adversely affect noise immunity. Other methods of implementing the synchronization function include using an open collector or open drain output device directly, or discreet devices to pull the ILIM/SYNC pin down. These do work but performance can suffer at high frequency because the ILIM/SYNC pin must rise to (VDD - 1.0 V) before the next switching cycle begins. Any time that this requires is directly subtracted from the maximum pulse width available and should be considered when choosing devices to drive ILIM/SYNC. Consequently, the lowest output capacitance devices work best. During a synchronization cycle, the current sink on the ILIM/SYNC pin becomes disabled when ILIM/SYNC is pulled below 1.0 V. The ILIM/SYNC current sink remains disabled until ILIM/SYNC reaches (VDD -1.0 V) This removes the load on the ILIM/SYNC pin to allow the voltage to slew rapidly depending on the ILIM resistor and any stray capacitance on the pin. To maximize this slew rate, minimize stray capacitance on this pin. 14 www.ti.com TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 APPLICATION INFORMATION Transient Comparators and Power Good The TPS4002x makes use of a separate pin, OSNS, to monitor output voltage for these two functions. In normal operation, OSNS is connected to the output via a resistor divider. It is important to make this divider the same ratio as the divider for the feedback network so that in normal operation the voltage at OSNS is the same as the voltage at FB, 0.69 V nominal. The PWRGD pin is an open drain output that is pulled low when the voltage at OSNS falls outside 0.69 V 4.6% (approximately). A delay has been purposely built into the PWRGD pin pulling low in response to an out of band voltage on OSNS, to minimize the need for filtering the signal in the event of a noise glitch causing a brief out of band OSNS voltage. The PWRGD signal returns to high when the OSNS signal returns to approximately 1% of nominal (0.69 V 1%). The transient comparators override the conventional voltage control loop when the output voltage exceeds a 4.6% window. If the output transition is high (i.e. load steps down from 90% load to 10 % load) then the HDRV gate drive is terminated, 0% duty cycle, the LDRV gate drive is turned on to sink output current until VOUT returns to within 1% of nominal. Conversely when VOUT drops outside the window (i.e. step load increases from 10% load to 90% load) HDRV increases to maximum duty cycle until VOUT returns to within 1% of nominal. (See Figure 7.) During start-up, the transient comparators control the state of PWRGD as previously described. However, the operation of the gate drive outputs is not affected. (See Figure 8) The transient comparators provide an improvement in load transient recovery time if used properly. In some situations, recovery time may be one half of the time required without transient comparators. Keep in mind that the transient comparator concept is a double-edged sword. While they provide improved transient recovery time, they can also lead to instability if incorrectly applied. For proper functionality, design a feedback loop for the converter that places the closed loop unity gain frequency at least five times higher than the 0 dB frequency of the output L-C filter. If not, the feedback loop cannot respond to the ring of the L-C on a transient event. The ring is likely to be large enough to disturb the transient comparators and the result is a power oscillator. Another helpful action is to ground the feedback loop divider and the OSNS divider at the SGND pin. Make sure both dividers measure the same physical location on the output bus. These help avoid problems with resistive drops at higher loads causing problems. Connecting OSNS to VDD disables the transient comparators. This also disables the PWRGD function. Alternatively, OSNS and FB can be tied together. This connection allows a proper PWRGD at startup, though transient performance diminishes. 4.6% 1% FB - 4.6% 10 s PWRGD 10 s -1% - 4.6% < 10 s 500 n s 500 n s SW 98 % Duty Cycle 0 % Duty Cycle 98 % Duty Cycle 0 % Duty Cycle UDG-03181 Figure 7. Duty Cycle Waveforms 15 TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 www.ti.com APPLICATION INFORMATION VDD 1.3 V 0.6 V 0.3 V SS/SD VOUT - 1% 500 ns VOUT 1.5 s Transient Comparators Enabled Transient Comparators Disabled UDG-03181 4 s PWRGD Figure 8. Transient Comparator Waveforms Layout Considerations Successful operation of the TPS4002x family of controllers is dependent upon the proper converter layout and grounding techniques. High current returns for the SR MOSFET's source, input capacitance, output capacitance, PVDD capacitance, and input bypass capacitors (if applicable), should be kept on a single ground plane or wide trace connected to the PGND (pin10) through a short wide trace. Control components connected to signal ground, as well as the PowerPad thermal pad, should be connected to a single ground plane connected to SGND (Pin 8) through a short trace. SGND and PGND should be connected at a single point using a narrow trace. Proper operation of Predictive Gate Drive technology and IZERO functions are dependent upon detecting low-voltage thresholds on the SW node. To ensure that the signal at the SW pin accurately represents the voltage at the main switching node, the connection from SW (pin 14) to the main switching node of the converter should be kept as short and wide as possible and should ideally be kept on the top level with the power components. If the SW trace must traverse multiple board layers between the TPS4002x and the main switching node, multiple vias should be used to minimize the trace impedance. Gate drive outputs, LDRV and HDRV (pins 11 and 15, respectively) should be kept as short as possible to minimize inductances in the traces. If the gate drive outputs need to traverse multiple board layers multiple vias should be used. Charge pump components, BOOT1, BOOT2, PVDD, and any input bypass capacitors (if required), should be kept as close as possible to their respective pins. Ceramic bypass capacitors should be used if the input capacitors are located more than a couple of inches away from the TPS4002X. If a bypass capacitor is not needed the trace from the input capacitors to VDD (pin2) should be kept as short and wide as possible to minimize trace impedance. If multiple board layers are traversed multiple vias should be used. 16 www.ti.com TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 APPLICATION INFORMATION Manufacturer's instructions should be followed for proper layout of the external MOSFETs. Thermal impedances given in the manufacturer's datasheets are for a given mounting technique with a specified surface area under the drain of the MOSFET. PowerPad package information can be found in the APPLICATION INFORMATION section of this datasheet. Refer to TPS40021 EVM-001 High Efficiency Synchronous Buck Converter with PWM Controller Evaluation Module (HPA009) User's Guide, (Literature No. sluu144A) for a typical board layout. The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depends on the size of the PowerPAD package. For a 16-pin TSSOP (PWP) package the area is 5 mm x 3.4 mm [3]. X: Minimum PowerPAD = 1.8 mm Y: Minimum PowerPAD = 1.4 mm Thermal Pad X 4,50 mm 6,60 mm 4,30 mm 6,20 mm 1 Y 8 Figure 9. PowerPAD Dimensions Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD Thermally Enhanced Package[3] for more information on the PowerPAD package. 17 TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 www.ti.com TYPICAL CHARACTERISTICS MAXIMUM DUTY CYCLE vs JUNCTION TEMPERATURE 99 1000 950 fOSC - Oscillator Frequency - kHz 98 Maximum Duty Cycle - % 900 850 800 750 700 650 600 550 500 VDD = 5 V, RT = 35 k 93 -50 -25 0 25 50 75 100 125 450 -50 -25 0 25 50 75 100 125 RT = 69.8 k RT = 35 k OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE 97 96 VDD = 3.3 V, RT = 69.8 k 95 94 TJ - Junction Temperature - C TJ - Junction Temperature - C Figure 10 SHUTDOWN SUPPLY CURRENT vs JUNCTION TEMPERATURE 0.700 0.675 695 0.650 0.625 0.600 0.575 VREF - Reference Voltage - mV 697 Figure 11 REFERENCE VOLTAGE vs JUNCTION TEMPERATURE IDD - Shutdown Supply Current - mA 693 691 689 0.550 0.525 0.500 -50 687 685 -25 0 25 50 75 100 125 683 -50 -25 0 25 50 75 100 125 TJ - Junction Temperature - C TJ - Junction Temperature - C Figure 12 Figure 13 18 www.ti.com TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 TYPICAL CHARACTERISTICS TIMING RESISTANCE vs SWITCHING FREQUENCY 1000 900 800 700 600 500 400 300 200 100 20 40 60 80 100 120 140 160 SOFT-START CURRENT vs JUNCTION TEMPERATURE 3.50 VIN = 3.9 V ISS - Soft-Start Sourcing Current - A 3.45 3.40 3.35 3.30 3.25 3.20 3.15 3.10 3.05 3.00 -50 fOSC - Frequency - kHz -25 0 25 50 75 100 125 RT - Timing Resistance - k TJ - Junction Temperature - C Figure 14 ILIM OFFSET VOLTAGE vs JUNCTION TEMPERATURE 20 15 VILIM - ILIM Offset Voltage - mV 10 5 0 -5 -10 -15 VDD = 4.9 V -20 -50 -25 0 25 50 75 100 125 VDD = 3.2 V VDD = 2.0 V VSS - Shutdown Threshold Voltage - V 0.30 0.29 0.28 Figure 15 SHUTDOWN THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE Enable 0.27 0.26 0.25 0.24 0.23 0.22 0.21 0.20 -50 -25 0 25 50 75 100 125 Disable TJ - Junction Temperature - C TJ - Junction Temperature - C Figure 16 Figure 17 19 TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 www.ti.com TYPICAL CHARACTERISTICS ILIM SINK CURRENT vs JUNCTION TEMPERATURE 200 198 196 IILIM - ILIM Sink Current - A 194 192 190 LDRV 188 186 184 182 180 -50 t - Time - 1 s/div -25 0 25 50 75 100 125 TJ - Junction Temperature - C SW VDD = 3 V RT = 69.8 k VOUT VDD = 3.3 V VOUT = 1.5 V fSW = 300 kHz Figure 18 VDD = 3.3 V VOUT = 1.5 V fSW = 300 kHz Figure 19. TPS40020 Discontinuous Mode (DCM) VOUT SS/SD VDD = 3.3 V VOUT = 1.5 V fSW = 300 kHz LDRV SW VOUT SW t - Time - 1 s/div t - Time - 20 ms/div Figure 20. TPS40020 IZERO Detection - DCM Figure 21. Output Current Fault Operation 20 www.ti.com TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 TYPICAL CHARACTERISTICS VDD = 3.3 V VOUT = 1.5 V fSW = 300 kHz ILOAD = 5 A VDD = 3.3 V VOUT = 1.5 V fSW = 300 kHz ILOAD = 5 A SS/SD PVDD SW VOUT PWRGD t - Time - 1 ms/div VOUT t - Time - 25 s/div Figure 22. Start-Up Operation Without Transient Comparators Figure 23. PVDD Hysteresis VDD = 3.3 V VOUT = 1.5 V fSW = 300 kHz ILOAD = 5 A SS/SD SD VDD = 3.3 V VOUT = 1.5 V fSW = 300 kHz ILOAD = 5 A COMP SW VOUT PWRGD t - Time - 1 ms/div t - Time - 200 s/div Figure 24. Start-Up Operation With Transient Comparators Figure 25. COMP Shutdown Operation 21 TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 www.ti.com TYPICAL CHARACTERISTICS VDD = 3.3 V VOUT = 1.5 V fSW = 300 kHz ILIM VDD = 3.3 V VOUT = 1.5 V fSYNC = 330 kHz SW SS/SD PWRGD LDRV t - Time - 1 s/div t - Time - 500 ns/div Figure 26. PWRGD Shutdown Operation Figure 27. External Synchronization 22 www.ti.com TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 REFERENCE DESIGN This design used the TPS40020 PWM controller to facilitate a step-down application from 3.3-V to 1.5 V. (see Figure 29) Design specifications include: D Input voltage: 2.5 V VIN 5.0 V D Nominal voltage: 3.3 V D Output voltage VOUT: 1.5 V D Output current IOUT: 20 A D Switching frequency: 300 kHz DESIGN PROCEDURE Setting the Frequency Choosing the optimum switching frequency is complicated. The higher the frequency, the smaller the inductance and capacitance needed, so the smaller the size, but then the the switching losses are higher, the efficiency is poorer. For this evaluation module, 300 kHz is chosen for reasonable efficiency and size. A resistor R4, which is connected from pin 7 to ground, programs the oscillator frequency. The approximate operating frequency is calculated in equation (3) R T (kW) + 37.736 10 * 5.09 (kW) f OSC(kHz) 3 (3) Using equation (2), RT is calculated to be 120 k and a 118-k resistor is chosen for 300 kHz operation. Inductance Value The inductance value can be calculated by equation (2). L (min) + V OUT f I RIPPLE 1* V OUT VIN(max) (4) where IRIPPLE is the ripple current flowing through the inductor, which affects the output voltage ripple and core losses. Based on 20% ripple current and 300 kHz, the inductance value is calculated to 0.76 H and a 0.75-H inductor (part number is CDEP149-0R7) is chosen. The ESR of this inductor is 1.1 m and the loss is 440 mW, which is approximately 1.5% of output power. C OUT(min) + I RIPPLE 8 f VRIPPLE (5) V ESR OUT + RIPPLE I RIPPLE (6) With 1% output voltage ripple, the needed capacitance is at least 114 F and its ESR should be less than 3.7 m. Three 2-V, 470-F, POSCAP capacitors from Sanyo are used. The ESR is 10 m each. The required input capacitance is calculated in equation (5). The calculated value is approximately 348 F. Three 6.0-V, 330-F POSCAP capacitors with 10 m ESR are used to handle 10 A of RMS input current. Additionally, two ceramic capacitors are used to reduce the switching ripple current. C IN(min) + I OUT(max) D(max) TS VRIPPLE (7) 23 24 C10 330 F C11 22 F C12 22 F TPS4002XPWP 1 2 VDD OSNS SW C2 1 F BOOT2 13 PVDD 12 5 LDRV 11 SS/SD PGND 10 7 PWRGD 9 8 SGND PWP RT C3 10 F R9 10 k C17 15 nF R1 8.66 k 6 C13 0.022 F R4 118 k COMP Q2 S7880DP R10 2.2 + C4 470 F + C5 470 F + C6 470 mF C7 10 F 14 FB L1 0.75 F C1 1 F 3 R5 8.66 k 4 C15 47 pF R17 30.1 k C15 47 pF HDRV 15 Q1 Si7858DP ILIM/SYNC BOOT1 16 R3 1.5 k 1.2 V 20 A TPS40020 TPS40021 + + + 3.3 V SLUS535B - MARCH 2003 - REVISED JANUARY 2004 C8 330 F C9 330 F R6 10 k R8 374 C16 8200 pF REFERENCE DESIGN Figure 28. Reference Design Schematic R2 10 k www.ti.com UDG-03031 www.ti.com TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 REFERENCE DESIGN Input and Output Capacitors The output capacitance and its ESR needed are calculated in equations (5) and (6). Compensation Design Voltage-mode control is used in this evaluation module, using R2, R7, R8, C14, C15, and C16 to form a Type-III compensator network. The L-C frequency of the power stage is approximately 4.9-kHz and the ESR-zero is around 34 kHz. The overall crossover frequency, f0db, is chosen at 43-kHz for reasonable transient response and stability. Two zeros fZ1 and fZ2 from the compensator are set at 2.4 kHz and 4 kHz. The two poles, fP1 and fP2 are set at 34 kHz and 115 kHz. The frequency of poles and zeros are defined by the following equations: f Z1 + f Z2 + f P1 + f P2 + 2p 2p 2p 2p 1 R7 1 R2 1 R8 1 R7 C14 C11 C11 C12 (assuming C14 C12) (assuming R2 R8) (8) (9) (10) (11) The transfer function for the compensator is calculated in equation (10). A(s) + s R2 (1 ) s C14 C14 R7) [1 ) s R7 C11 C12 (R2 ) R3)] (1 ) s R8 C11) (12) 1 ) C12 ) s C14 Figure 30 shows the close loop gain and phase. The overall crossover frequency is approximately 30 kHz. The phase margin is 57. OVERALL GAIN AND PHASE vs OSCILLATOR FREQUENCY 50 40 30 20 Gain - dB 10 0 -10 -20 -30 -100 -40 -50 100 -150 100 k Phase 0 100 Phase - Gain 150 200 50 -50 1k 10 k fOSC - Oscillator Frequency - kHz Figure 29. 25 TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 www.ti.com REFERENCE DESIGN MOSFETs and Diodes For a 1.5-V output voltage, the lower the RDS(on) of the MOSFET, the higher the efficiency. Due to the high current and high conduction loss, the MOSFET should have very low conduction resistance (RDS(on)) and thermal resistance. Si7858DP is chosen for its low RDS(on) (between 3 m and 4 m) and Power-Pak package. Current Limiting Resistor R3 sets the over current limit threshold. The RDS(on) of the upper MOSFET is used as a current sensor. The current limit is initialized at 40% above the maximum output current, IOUT(max), which is 28 A. Then R3 can be calculated in equation (11) and yields a value of 1.43 k. I LIM + K 20 V REF R4 + 20 I OUT 0.7 V + 118.6 (mA) 118 kW 1.5 4 (mW) 28 A + 1.43 (kW) I LIM (mA) (13) R3 + where RDS(on) I LIM (mA) + (14) D D D D RDS(on) is the on-resistor of Q1 (4 m) Temperature coefficient, K=1.5 VREF=0.7 V R4=118 k Voltage Sense Regulator R1 and R2 operate as the output voltage divider. The internal reference voltage (VREF) is 0.7 V. The relationship between the output voltage and divider is described in equation (8). Using a 10-k resistor for R2 and 1.5-V output regulation, R1 is calculated as 8.66 k. V REF R1 + V OUT 1.5 V + 0.7 V + + 8.66 kW R1 ) R2 R1 R1 ) 10 kW (15) Transient Comparator The output voltage transient comparators provide a quick response, first strike, approach to output voltage transients. The output voltage is sensed through a resistor divider at the OSNS pin, using R5 and R6 shown in Figure 28. If an overvoltage condition is detected, the HDRV gate drive is shut off and the LDRV gate drive is turned on until the output is returned to regulation. Similarly, if an output undervoltage condition is sensed, the HDRV gate drive goes to 95% duty cycle to pump the output back up quickly. The voltage divider should be exactly the same as resistors R1 and R2 discussed previously. Resistor R5=8.66 k and R6=10 k in this evaluation module. 26 www.ti.com TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 REFERENCE DESIGN TEST RESULTS Efficiency Curves The tested efficiency at different loads and input voltages are shown in Figure 30. The maximum efficiency is as high as 93% at 1.5-V output. The efficiency is around 88% when the load current (ILOAD) is 20 A. EFFICIENCY vs OUTPUT LOAD CURRENT VIN = 2.5 V 0.95 0.90 Efficiency - % 0.85 VIN = 4.0 V 0.80 VIN = 5.0 V VIN = 3.3 V 0.75 0.70 0 5 10 ILOAD - Load Current - A 15 20 Figure 30. Typical Operating Waveforms Typical operating waveforms are shown in Figure 31 and 32. VIN = 3.3 V ILOAD = 20 A VIN = 3.3 V ILOAD = 20 A VSW (2 V/div) VOUTac (10 mV/div) t - Time - 1 s/div t - Time - 1 s/div Figure 31 Figure 32 27 TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 www.ti.com REFERENCE DESIGN Transient Response and Output Ripple Voltage The output ripple is about 15 mVP-P at 20-A output. When the load changes from 4 A to 20 A, the overshooting voltage is about 35 mV. Figures 33 and 34 show the transient waveform with and without the transient comparator. Using the transient comparator yields a settling time of 10-s faster than without. The output ripple is about 15 mVP-P at 20-A output which is shown in Figure 33. When the load changes from 0 A to 13 A, the overshoot voltage is approximately 80 mV, and the undershoot is is approximately 60 mV as shown in Figure 35. When the transient comparator is triggered, the powergood (PWRGD) signal goes low. VOUTac (50 mV/div) IOUT (10 A/div) t - Time - 200 s/div VIN = 3.3 V WIth Transient Comparator VIN = 3.3 V WIthout Transient Comparator WIth Transient Comparator WIthout Transient Comparator IOUT (10 A/div) IOUT (10 A/div) t - Time - 10 s/div t - Time - 10 s/div Figure 33. Transient Response Undershoot Figure 34. Transient Response Overshoot 28 www.ti.com TPS40020 TPS40021 SLUS535B - MARCH 2003 - REVISED JANUARY 2004 REFERENCE DESIGN VPWRGD (2.5 V/div) VOUTac (100 mV/div) IOUT (10 A/div) t - Time - 200 s/div Figure 35. Transient Response 29 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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